This invention relates to switching or multiplexing structures for sending and retrieving variable amounts of data from memory or other circuit elements within integrated circuit devices. Devices of the type that are sometimes known as structured application-specific integrated circuits (“structured ASICs”) may particularly benefit.
A possible use of structured ASIC technology is to produce ASICs that are functionally equivalent to programmed field-programmable gate arrays (“FPGAs”). After a logic design has been adequately “proven” in an FPGA, the design may be “migrated” to a structured ASIC. Structured ASICs offer several key performance advantages over FPGAs, primarily in the areas of power reduction, clock performance, manufacturing costs, and core density. A potential competing concern that might reduce such benefits of the migration from an FPGA to an ASIC is maintaining equivalent functionality between the ASIC and the FPGA.
For instance, in many FPGA devices, it is desirable for the memory to be designed to support multiple bus width configurations. To support the multiple bus width configurations, the FPGA requires large multiplexing, or muxing, structures to handle the proper selection of data to be read from or written to memory. However, directly transferring the multiple bus width configurations from the FPGA to the corresponding ASIC would degrade performance by leading to a bigger layout area, a more complex design, and an increased loading on the input and output muxing paths.
Accordingly, when the FPGA has the flexibility of multiple bus width configurations, it is not desirable to directly transfer the multiple data bus width configurations from the FPGA to the corresponding ASIC. Such direct transferring would at least partially defeat the purpose of having an ASIC, which is designed to be smaller and faster than the FPGA.
It is therefore desirable to have a muxing structure within an ASIC that does not degrade performance and that can provide equivalent functionality to an FPGA having multiple bus width configurations.